The JK flip-flop comes in integrated circuit form in a multitude of configurations. However, the most common logic symbols are shown below. The preset and the clear are asynchronous and active low. The "J" input is synchronous and sets the "Q" output while the "K" input resets the "Q" output and is also synchronous. The two types shown below trigger on the edge of the clock, where the positive edge triggered device triggers on the rising edge, and the negative edge triggered device triggers on the falling edge of the clock input. The "Q" output is simply the inverse of the "Q" output.
|Positive edge triggered||Negative edge triggered|
The JK flip-flop is unique from other types of latches in that the state, in which both "J" and "K" are active, is not an invalid state. When both "J" and "K" are active the flip-flop goes into toggle mode and the output switches state on each active clock edge.
To fully appreciate the JK flip-flop one needs to follow the progression sequence from the simplest latch.
Above you see what has to be the simplest possible latch. It latches very well. However, there is no way, short of shorting the output, to change its state. A much better way to control a latch is shown below. This latch is known as an SR latch for its set reset function.
The SR latch shown above has active high set and reset inputs. A high on set causes a low output on "Q" resulting in a high on "Q". Likewise, a high on reset causes a low output on "Q" resulting in a high on "Q".
The only problem with the logic of an SR latch is that when both set and reset are active, "Q" and "Q" are both the same (Low in this case) which is an invalid state.
If one would like to synchronize the functions of the SR latch, then a clock needs to be added to the circuit. Below is a clocked SR latch.
The clocked SR latch only allows the outputs to change when the clock is active. For this reason, the clocked SR latch is sometimes referred to as a transparent latch. In other words, the output reflects the input when the clock is active and is, therefore, transparent. When the clock is inactive, the outputs are latched, and any changes to "S" or "R" inputs are ignored.
The positive edge triggered SR latch makes use of the delay present in the inverter to temporarily satisfy the input logic to the AND gate which produces a very short pulse, just enough time to latch the output. This happens only when the clock input goes from low to high. The output of the inverter is already high, and by the time the inverter output goes low, the AND gate has already seen two high inputs and responded with a high output, which quickly goes back low when the inverter output goes low.
The JK flip-flop is a clever way of eliminating the invalid state discussed earlier regarding the SR latch. By cross coupling the outputs to the inputs through logic gates, the condition where both synchronous inputs are active at the same time simply causes the outputs to change state, thus toggling the output.